Semiconductors
10 Marvell engineering leaders
These ten engineering leaders hold or have held director-level and higher engineering roles at Marvell Technology, with titles such as director of engineering and senior director of engineering. A reader can learn how engineering leaders build and run their teams in semiconductor companies.
Professionals to explore
01—10Amit Sharma
LinkedInExperience: Design Engineering Director · Marvell Technology
Design Engineering Director at Marvell Technology since 2018; the profile describes leading design and verification teams for the Data Center Engineering (DCE) Business Unit, driving development of hardware accelerators, Data Processing Units (DPUs) and SmartNIC products, with responsibility for end-to-end SoC design leadership. Former Sr. Design Engineering Manager at Cadence (2013–2018).
Duncan Kwok
LinkedInExperience: Senior Director of Engineering · Marvell Technology
Senior Director of Engineering at Marvell Technology since January 2013, based in Santa Clara, and former Director of Engineering at Marvell Technology in rows dated 2008–2013 and 2006–2008. The profile headline gives the role as Senior Director of Engineering at Marvell Semiconductor. Former Technical manager at Intel (1999–2006).
James Chiu
LinkedInExperience: Senior Director of Engineering · Marvell Technology
Senior Director of Engineering at Marvell Technology since April 2023, a role the profile lists at the Director level in the Engineering and Technical department. Former Director of Engineering (2008–2023) and Senior Design Engineering Manager (2001–2008) at Marvell Technology, and former Principal Engineer at Texas Instruments (1993–2000).
Paolo Pascale
LinkedInExperience: Senior Director of Engineering · Marvell Technology
Senior Director of Engineering at Marvell Technology since May 2023, in Pavia, Lombardia, Italy; the profile headline describes the role as Senior Director of Digital Design Engineering. Former Director Digital Design Engr at Marvell Technology (2021–2023) and at Inphi Corporation (2021), and former Senior Manager of SerDes Digital Engineering at eSilicon (2017–2020).
Raymond Peng
LinkedInExperience: Senior Director ASIC Design Services · Marvell Technology
Former Senior Director ASIC Design Services at Marvell Technology (2020–2024); the profile describes serving as a technical leader and manager in the Marvell ASIC Design Services teams executing in 5nm, 7nm and 14nm technologies. Former Director ASIC Design Center Design Services at Broadcom (2016–2020) and at IBM (2014–2016).
Shawn Kermanchi
LinkedInExperience: Senior Director of Engineering, Toronto site lead at Marvell · Marvell Technology
Senior Director of Engineering, Toronto site lead at Marvell, at Marvell Technology since 2022. Former VP of Engineering, Toronto site lead at Rianta Solutions Inc. (2017–2022), former VP of ASICs Development at Istuary IoT Labs Inc. (2016–2017) and former Senior Director of Engineering at Qualcomm (2009–2016).
Tarun Setya
LinkedInExperience: Senior Director of Engineering · Marvell Technology
Senior Director of Engineering at Marvell Technology since October 2024 and former Director Of Engineering there (2021–2024). The profile describes leading global chip developments for 1.6T/3.2T connectivity solutions from concept development to final silicon, and leading a global team of digital design and DFT engineers. Former Director Of Engineering at Inphi Corporation (2020–2021).
Vandana Goel
LinkedInExperience: Senior Director, Hardware Engineering · Marvell Technology
Senior Director, Hardware Engineering at Marvell Technology since March 2026, a role the profile lists at the Director level in the Engineering and Technical department. Former Director of Engineering at Intel in rows dated 2018–2022 and 2022–2026, and former Program Manager at MediaTek (2015–2018).
Victor Hart
LinkedInExperience: Director of Engineering · Marvell Technology
Director of Engineering at Marvell Technology since 2013; the profile headline ties the role to Compute and Custom Solutions and describes leading multiple teams of engineers on all aspects of network coprocessor block development with custom design and third party IP. Former Sr. Principal Hardware Verification Engineer at Emulex, an Avago Technologies Company (2005–2013).
Yuan Yao
LinkedInExperience: Director of Engineering · Marvell Technology
Director of Engineering at Marvell Technology since 2018, based in Irvine, California; the profile headline gives the role as Engineering Director, Analog/Mixed-Signal IC Design, at Marvell. The profile lists the role at the Director level in the Engineering and Technical department.
Choose the right perspective
Pick the person whose engineering area matches your question, since digital design, analog and mixed-signal design, ASIC services and site leadership involve different problems. Check whether the relevant Marvell role is current before asking about present-day roadmaps or team structure.
Questions to take into the conversation
- 01How do you staff and coordinate a chip program across design, verification and DFT teams in several countries?
- 02What does the path from concept to final silicon look like for your products, and where do schedules usually slip?
- 03How do you decide when to use third-party IP versus building blocks in-house?
Reaching Marvell engineering leaders
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About this directory
This is a professional research starting point based on business profile data retrieved on . Titles and companies reflect that source snapshot and may describe past or present roles. Check the linked profiles for current details. Inclusion does not imply Instant Expert membership or availability.
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