Semiconductors
10 ASIC design verification experts
These ten professionals have held ASIC and SoC design verification roles as engineers, leads, managers and directors at chip and silicon companies. A reader can learn how design verification teams are organized and run inside chip companies.
Professionals to explore
01—10Anish Patel
LinkedInExperience: Senior Manager - Silicon Design Engineering · AMD
Senior Manager - Silicon Design Engineering at AMD since 2024, a role in which the profile says this person leads a global DV team effort verifying SouthBridge IPs. Former Manager - Silicon Design Engineering at AMD (2021–2024) and Engineering Manager DV Lead at Cortina Access (2021).
Jigneshkumar Patel
LinkedInExperience: Sr Verification Project Lead · Intel
Former Sr Verification Project Lead at Intel (2016–2025), and Manager Silicon Design Engineering at AMD since 2026. The profile says the person led critical verification projects and was recognized for implementing debug tools that reduced file sizes by 60% and debug time by 40%.
Jitendra Kushwaha
LinkedInExperience: Director GPU SoC Verification · Intel
Former Director GPU SoC Verification at Intel (2021–2024), and Sr Director SoC Engineering at Synopsys Inc since 2024. Former Sr Engineering Manager(R&D) Manager(R&D) at Synopsys Inc (2015–2021) and Sr. IC Engineer at Magnachip Semiconductor (2007–2011).
Joydeep Bhattacharyya
LinkedInExperience: Senior Engineering Manager IP Verification · Intel
Former Senior Engineering Manager IP Verification (2024–2025) and Technical Leader DV Architect (2016–2021) at Intel. Sr Manager Silicon Design Engineering at AMD since 2025. The profile cites 12+ successful tape-outs across technical leadership and engineering management roles.
Karthiga Selvam
LinkedInExperience: Design Verification Engineering Manager · Intel
Design Verification Engineering Manager at Intel since 2024. Former IP Design Verification Lead Ethernet Products Group Silicon Engineering at Intel (2020–2023), Associate Director IP Verification Management at Samsung Semiconductor (2018–2020) and Staff Engineer Manager, Design Verification at Infinera (2016–2018).
Krupa Shah
LinkedInExperience: Verification Lead · Intel
Former Verification Lead at Intel (2017–2025), and Technical Leader at Cisco Systems since 2025. The profile describes testbench development with UVM and System Verilog and experience with PCIe Gen 2/3/4, DDR Phy and AMBA standards. Former Sr. Design Verification Engineer at SmartPlay Technologies - An Aricent Company (2013–2014).
Manem Santosh Kumar
LinkedInExperience: Verification Manager · Broadcom
Verification Manager at Broadcom since 2019, with a Staff Engineer role at Broadcom listed since 2014. Former ASIC Engineer at Brocade (2012–2014). The profile lists VLSI front-end verification, development of verification environments, and coverage driven and constraint random verification.
Pavan Yeluri
LinkedInExperience: Design Verification Manager, Silicon · Google
Design Verification Manager, Silicon at Google since 2023. Former Senior Design Verification Manager at Intel (2021–2023), Senior Design Verification Engineer at NVIDIA (2018–2021) and Senior Design Engineer (Design Verification) at Xilinx (2011–2018).
Saravana Venkataraman
LinkedInExperience: Design Verification Lead · Oracle
Former Design Verification Lead at Oracle (2010–2015), and Principal Engr Sr.Manager at Samsung Semiconductor since 2023. The profile says the person led the verification of Control, ShaderIO, GFX Backend and Memory Subsystems on multiple Samsung/AMD GPU projects and was project DV lead for two GPU projects.
Shailesh Dave
LinkedInExperience: Sr Director ASIC Verification · Astera Labs
Sr Director ASIC Verification at Astera Labs since 2025, and Director Design Verification at Astera Labs from 2022 to 2026. The profile describes leading a team for verification of a system consisting of multiple FPGAs and ASIC. Former Principal Verification Engineer at AMD Pensando (2019–2021) and Sr verification Manager at Quantenna Communications (2017–2019).
Choose the right perspective
Match the person's seat to your question, since leading a verification organization differs from building testbenches and verifying individual IP blocks. Also consider the kind of design behind your decision, because IP, subsystem and full SoC verification raise different planning and coverage problems.
Questions to take into the conversation
- 01How do you build a verification plan and decide when coverage is good enough to sign off for tape-out?
- 02How do you split verification work between IP, subsystem and full-chip levels, and where do bugs most often slip through?
- 03How do you size and organize a design verification team as chip complexity and schedule pressure grow?
Reaching ASIC design verification experts
How can I contact one of these ASIC design verification experts?
Pick one of the 10 people on this page and choose "Book a paid call", or describe your project to find others. You offer a fee for a 15-minute call or a written answer, Instant Expert finds the person's work email and sends the invitation, and they decide whether to accept. The list covers 6 companies, including AMD, Intel and Broadcom, based on profile data retrieved on October 4, 2026. Being listed here doesn't mean someone has agreed to take calls.
How much does it cost to reach ASIC design verification experts?
You choose the offer, starting at $5 per person. It includes Instant Expert's 20% fee, so an offer that pays the person $100 costs you $125. You're charged only when the person books the call or sends the answer.
What if they don't reply?
You pay nothing. Instant Expert sends follow-up reminders, and if the person hasn't booked or answered within 7 days, the request expires and any hold on your card is released. You can invite several of the 10 people on this list at once and cap your total spend, so you pay only for the ones who accept.
About this directory
This is a professional research starting point based on business profile data retrieved on . Titles and companies reflect that source snapshot and may describe past or present roles. Check the linked profiles for current details. Inclusion does not imply Instant Expert membership or availability.
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