Semiconductors
10 semiconductor test engineering experts
These ten professionals have held test engineering manager and director roles at semiconductor companies. A reader can learn how semiconductor companies organize test engineering teams and move test programs from development into production.
Professionals to explore
01—10Ayesh Fernando
LinkedInExperience: Test Engineering Manager · Texas Instruments
Test Engineering Manager at Texas Instruments since May 2016, and Program and Test Engineering Manager there from 2014 to 2016. The profile describes managing a team of 8 to 10 test engineers to develop and release production test solutions for Precision Amplifier Products. Other listed Texas Instruments roles include Product Engineering Manager (2008–2014).
Binesh George
LinkedInExperience: Test Engineering Manager · Texas Instruments
Test Engineering Manager at Texas Instruments since March 2016. The profile summary describes experience in mixed signal and digital ATE testing for wafer sort, final test, hardware development and product support. Other listed roles include Sr. Manager at Lattice Semiconductor (2015–2016) and Sr. Test Engineer at Silicon Image (2004–2009).
Byron Villanueva
LinkedInExperience: Product Test Engineering Manager · Intel
Product Test Engineering Manager at Intel since May 2018. The profile describes an expat assignment in Dalian, China to build and manage a Sort Test Engineering team to help enable 3D NAND Flash technology development, and managing sort readiness for new technology introductions. Other listed roles include Probe Product Reliability Manager at IM Flash (2013–2018).
Darren Fan
LinkedInExperience: Senior Test Engineering Manager · Renesas Electronics
Senior Test Engineering Manager at Renesas Electronics since April 2021. The profile describes leading the test engineering department (Asia Test Center), supporting global NPI and sustaining programs for high-volume PMIC and mixed-signal products. Also Test Engineering Manager at Dialog Semiconductor (2019–2021) and Group Team Lead Senior Test Engineer there (2015–2019).
Gabriela Nunes
LinkedInExperience: Test Engineering Manager · Qorvo, Inc.
Test Engineering Manager at Qorvo, Inc. since May 2026, with the listing also showing Sr. Probe Test Engineer at Qorvo, Inc. since 2015. The profile describes developing, sustaining and enhancing high volume test solutions for active and passive products, and test design and setup for wafer manufacturing from new product development through the product lifecycle.
Himanshu Tiwari
LinkedInExperience: Test Engineering Manager · Intel
Former Test Engineering Manager at Intel (2019–2024), and Test Engineering Manager at Texas Instruments since May 2024. The listing also shows Lead Test Engineer at Texas Instruments (2015–2019), Test Engineer Lead at NXP acquires Freescale Semiconductor (2012–2014) and Validation Engineer at NXP acquires Freescale Semiconductor (2014–2015).
Kalpesh Vaghasiya
LinkedInExperience: Test Engineering Manager · Micron Technology
Former Test Engineering Manager at Micron Technology (2019–2022) and Product Test Development Engineering Manager there (2010–2019); DRAM Product Engineering Manager at Micron since 2022. The profile lists work as DDR5/GDDR6 ATE manager leading a high speed testing team and as DDR5/DDR4/GDDR6 wafer sort manager leading a wafer sort test engineering team.
Robert Boos
LinkedInExperience: Test Engineering Manager · onsemi
Former Test Engineering Manager at onsemi (2000–2018). The profile describes developing both characterization and production test programs for probe and final test using a wide variety of ATE equipment, and serving as a project lead managing a team of engineers supporting the ATE test development of a multi-chip project. Other listed roles include Staff Test Engineer at NXP acquires Freescale Semiconductor (1993–2000).
Steve Mani
LinkedInExperience: Test Engineering Manager - Senior Member of Technical Staff · AMD
Test Engineering Manager - Senior Member of Technical Staff at AMD since March 2026, and Test Engineering Manager - Member of Technical Staff there from 2022 to 2026. The profile describes developing manufacturing and characterization test programs for APU Kaveri and collaborating with test teams on ATE platforms. Other listed AMD roles include Senior Product Development Engineer (2019–2022).
Tyler Waite
LinkedInExperience: Director, Test Solutions Engineering · Micron Technology
Director, Test Solutions Engineering at Micron Technology since November 2025. The profile describes leading a team of engineers to provide wafer level test solutions across Micron's DRAM product portfolio. Other listed Micron roles include R&D Probe Test Engineering Manager (2015–2026), TSE Technology Development Senior Manager (2019–2026) and NAND and R&D Test Engineering Lead (2011–2015).
Choose the right perspective
Match the person's seat to your question, since leading a test engineering group differs from writing and debugging test programs on the tester. Also consider product type and test stage, because memory, processors, analog and RF parts and wafer-level versus final test raise different problems.
Questions to take into the conversation
- 01How do you balance test coverage against test time and cost when releasing a new product to production?
- 02How should wafer probe and final test responsibilities be split between in-house teams and manufacturing sites?
- 03What do you look at first when a product's test yield drops in production?
Reaching semiconductor test engineering experts
How can I contact one of these semiconductor test engineering experts?
Pick one of the 10 people on this page and choose "Book a paid call", or describe your project to find others. You offer a fee for a 15-minute call or a written answer, Instant Expert finds the person's work email and sends the invitation, and they decide whether to accept. The list covers 7 companies, including Texas Instruments, Intel and Renesas Electronics, based on profile data retrieved on October 4, 2026. Being listed here doesn't mean someone has agreed to take calls.
How much does it cost to reach semiconductor test engineering experts?
You choose the offer, starting at $5 per person. It includes Instant Expert's 20% fee, so an offer that pays the person $100 costs you $125. You're charged only when the person books the call or sends the answer.
What if they don't reply?
You pay nothing. Instant Expert sends follow-up reminders, and if the person hasn't booked or answered within 7 days, the request expires and any hold on your card is released. You can invite several of the 10 people on this list at once and cap your total spend, so you pay only for the ones who accept.
About this directory
This is a professional research starting point based on business profile data retrieved on . Titles and companies reflect that source snapshot and may describe past or present roles. Check the linked profiles for current details. Inclusion does not imply Instant Expert membership or availability.
Request a correction or removal